What is the signal conversion process in HDMI to eDP?

The signal conversion process in HDMI to eDP involves a multi-stage transformation where the HDMI source’s TMDS (Transition Minimized Differential Signaling) stream is decoded, color-space converted, and re-encoded into eDP’s embedded DisplayPort packetized data, all while managing clocking, voltage levels, and link training. This is not a simple cable swap; it requires an active bridge chip, typically from vendors like Parade Technologies, NXP, or Analogix, which handles protocol translation, resolution scaling, and backlight control. For instance, the hdmi to edp display adapter uses a dedicated controller to convert HDMI 1.4 or 2.0 signals into eDP 1.2 or 1.4, supporting up to 4K at 60Hz with 8-bit color depth. Let’s break down the actual steps, data rates, and real-world constraints.

HDMI Input Stage: TMDS Decoding and Clock Recovery

HDMI transmits video, audio, and auxiliary data using three TMDS data channels and one clock channel. Each channel carries 10-bit symbols at a rate of up to 6 Gbps per lane for HDMI 2.0, totaling 18 Gbps for 4K60 4:4:4. The conversion process begins with the bridge chip’s receiver terminating the differential signals at 100 ohms and recovering the pixel clock from the TMDS clock channel. For example, at 1080p60, the pixel clock is 148.5 MHz; for 4K60, it’s 594 MHz. The chip must lock a PLL (Phase-Locked Loop) to this clock, with jitter tolerance typically below 0.6 UI (Unit Interval) per HDMI specification. The TMDS decoder then deserializes the 10-bit symbols into 8-bit pixel data, separating R, G, B components and the horizontal/vertical sync signals. If the HDMI source uses YCbCr 4:2:2 or 4:2:0 chroma subsampling, the bridge must perform chroma upsampling to 4:4:4 before proceeding, using a 2D interpolation filter with a coefficient set that matches the SMPTE 274M standard. This step adds 1–2 lines of latency, depending on the filter tap count.

Color Space Conversion and Bit Depth Mapping

eDP natively uses RGB 4:4:4 with 6, 8, or 10 bits per color, while HDMI can carry RGB, YCbCr, or xvYCC. The conversion process must map the HDMI color space to eDP’s RGB domain. For YCbCr to RGB, the chip applies a 3x3 matrix multiplication with coefficients from ITU-R BT.601 or BT.709, depending on the HDMI source’s colorimetry metadata. For example, BT.709 uses: R = Y + 1.5748 * (Cb - 128), G = Y - 0.1873 * (Cb - 128) - 0.4681 * (Cr - 128), B = Y + 1.8556 * (Cr - 128). This is done in fixed-point arithmetic with 12-bit precision to avoid rounding errors. If the HDMI input is 10-bit but the eDP panel supports only 8-bit, the chip dithers using a 2D spatial-temporal algorithm (e.g., Floyd-Steinberg) to reduce banding, with a dithering noise amplitude of ±1 LSB. Conversely, if the panel is 10-bit and the HDMI is 8-bit, the chip can expand via zero-padding or use a 3D LUT (Look-Up Table) for gamma correction. The eDP specification requires gamma values of 2.2 or 2.4, so the chip may apply a gamma mapping table stored in its firmware, with 256 or 1024 entry points, depending on the precision.

eDP Encoding: Packetization, Link Training, and AUX Channel

eDP uses a packetized data structure similar to DisplayPort, where video data is encapsulated into Main Link packets with 8B/10B encoding. The conversion process takes the RGB pixel stream and serializes it into eDP lanes, which can be 1, 2, or 4 lanes, each running at 1.62, 2.7, or 5.4 Gbps (HBR2) for eDP 1.4. The bridge chip must negotiate link training with the eDP panel via the AUX channel, a bidirectional half-duplex link running at 1 Mbps. During training, the chip sends a training pattern (e.g., TPS1, TPS2, TPS3) and adjusts the pre-emphasis and voltage swing levels (typically 0.4V to 1.2V peak-to-peak) based on the panel’s equalization feedback. The process takes about 5–10 ms, with a maximum of 5 retries per the eDP standard. The chip then packs the pixel data into micro-packets, each containing 48 or 64 bits of pixel data, with a header that includes the video timing parameters (HTotal, VTotal, HActive, VActive). For example, for 1920x1080 at 60Hz, the HTotal is 2200, VTotal is 1125, so the chip must generate a blanking interval of 280 pixels per line and 45 lines per frame. The eDP stream also includes secondary data packets for backlight control (e.g., PWM frequency, brightness level) and panel self-refresh (PSR) commands, which the bridge chip must parse from the HDMI source’s InfoFrames or vendor-specific data.

Backlight Control and Power Sequencing

eDP panels require a separate backlight driver, typically a PWM signal, which the bridge chip generates from the HDMI source’s DDC/CI (Display Data Channel Command Interface) or from a dedicated PWM pin. The conversion process maps the HDMI’s backlight control protocol (e.g., from a monitor’s menu) to the eDP’s standard backlight control via the AUX channel, using the eDP Backlight Control (BLU) commands. For example, a brightness level of 50% in HDMI corresponds to a PWM duty cycle of 50% at a frequency of 200 Hz to 1 kHz, depending on the panel’s spec. The chip also manages power sequencing: it must assert the eDP panel’s power enable pin (PWR_EN) before the HPD (Hot Plug Detect) signal, with a delay of 10–50 ms per the eDP timing diagram. The bridge chip’s firmware includes a state machine that transitions through power-on (P0), power-off (P3), and standby (P2) states, with each state requiring specific voltage levels (e.g., 3.3V for VDD, 1.8V for VDDIO). If the HDMI source is removed, the chip must initiate a graceful shutdown, deasserting the backlight first, then the main link, within 100 ms to avoid panel damage.

Data Rate and Bandwidth Constraints

The conversion process is bottlenecked by the HDMI input bandwidth and the eDP output link rate. For HDMI 1.4, the maximum TMDS clock is 340 MHz, supporting 4K30 4:4:4 or 4K60 4:2:0. For HDMI 2.0, the clock is 600 MHz, supporting 4K60 4:4:4. The eDP link must match or exceed this bandwidth. For example, a 4-lane eDP 1.4 at 5.4 Gbps per lane provides 17.28 Gbps of raw bandwidth, but after 8B/10B encoding overhead (20%), the effective data rate is 13.824 Gbps. For 4K60 4:4:4 8-bit, the pixel data rate is 594 MHz * 24 bits = 14.256 Gbps, which exceeds the eDP link’s effective rate. So the bridge chip must use compression, such as DSC (Display Stream Compression) 1.2, which is supported in eDP 1.4. DSC compresses the video stream with a ratio of 2:1 to 3:1, using a predictive coding algorithm with a slice-based approach. For 4K60, DSC reduces the data rate to about 7 Gbps, fitting within the eDP link. The chip must implement the DSC encoder, which adds 1–2 lines of latency and requires a dedicated SRAM buffer of 64 KB per slice. The compression ratio is set by the panel’s EDID, which specifies the DSC capability and the target bit rate.

Signal Integrity and Jitter Management

HDMI and eDP use different electrical signaling. HDMI uses TMDS with 3.3V swing, while eDP uses DisplayPort’s AC-coupled differential signaling with 0.4V to 1.2V swing. The conversion process includes a level shifter and a re-driver that adjusts the voltage swing and pre-emphasis. The bridge chip’s transmitter must meet eDP’s eye diagram requirements: a minimum eye opening of 0.2V at the receiver, with a jitter budget of 0.3 UI total. The chip uses a spread-spectrum clock (SSC) to reduce EMI, typically with a modulation rate of 30–33 kHz and a deviation of 0.5% to 1%. The HDMI input jitter (e.g., from a long cable) is filtered by the PLL, which has a bandwidth of 1–5 MHz. If the jitter exceeds 0.6 UI, the chip may lose lock, forcing a re-sync. The chip also includes a cable equalizer that compensates for HDMI cable losses, which can be up to 20 dB at 3 GHz for 10-meter cables. The equalizer uses a CTLE (Continuous-Time Linear Equalizer) with adjustable gain from 0 to 12 dB, set during the initial link detection.

EDID and HDCP Pass-Through

The conversion process must handle EDID (Extended Display Identification Data) from the eDP panel and pass it to the HDMI source. The bridge chip reads the panel’s EDID via the AUX channel, which contains the supported resolutions, timings, and color depths. For example, a 15.6-inch 4K eDP panel’s EDID might list 3840x2160 at 60Hz with 8-bit, and a DSC flag. The chip stores this EDID in its internal EEPROM and presents it to the HDMI source via the DDC line. If the HDMI source requests HDCP 1.4 or 2.2 content protection, the bridge chip must decrypt the HDMI stream and re-encrypt it for eDP. HDCP 2.2 uses a 128-bit AES cipher, requiring the chip to have a dedicated cryptographic engine that processes 16-byte blocks in 4 clock cycles. The chip must also authenticate with the eDP panel’s HDCP receiver, which involves a 5-message exchange over the AUX channel. If the panel does not support HDCP, the chip must either block the content or fall back to a lower resolution, depending on the source’s policy. The HDCP pass-through adds about 2 ms of latency and requires the chip to have a unique private key stored in fuses.

Power Consumption and Thermal Management

The bridge chip’s power consumption varies with resolution and link speed. For a typical 4K60 conversion, the chip draws about 1.5W to 2.5W, depending on the process node (e.g., 28nm or 40nm). The power is distributed across the TMDS receiver (0.3W), the color space converter (0.2W), the DSC encoder (0.5W), the eDP transmitter (0.4W), and the PLLs (0.1W). The chip must dissipate heat through a thermal pad or a small heatsink, with a maximum junction temperature of 85°C. If the ambient temperature is 50°C, the chip’s thermal resistance must be below 20°C/W. The conversion process also includes power management features like dynamic voltage scaling, where the core voltage drops from 1.2V to 0.9V during idle periods, reducing power by 30%. The chip’s firmware can also disable the DSC encoder if the panel supports the full bandwidth without compression, saving 0.5W.

Practical Implementation and Real-World Testing

In a real-world setup, the conversion process is validated using a pattern generator and an oscilloscope. For example, a 4K60 HDMI source outputting a color bar pattern is connected to the bridge chip, and the eDP output is probed at the panel connector. The eye diagram shows a 0.35V opening at 5.4 Gbps, with a jitter of 0.2 UI. The latency from HDMI input to eDP output is measured at 3.5 lines, or about 0.15 ms at 4K60. The chip’s firmware must handle edge cases like hot-plug events, where the HDMI source is disconnected and reconnected. The chip’s HPD (Hot Plug Detect) pin must assert within 100 ms of the eDP panel being powered, and the link training must complete within 50 ms. If the panel’s EDID changes (e.g., after a firmware update), the chip must re-read it and re-negotiate the link. The conversion process also includes a fallback mode: if the eDP panel cannot handle the requested resolution, the chip downscales the HDMI input using a 2D scaler with bilinear or bicubic interpolation, which adds 2–4 lines of latency and requires a frame buffer of 4 MB for 4K.

Protocol Overhead and Latency Budget

The conversion process introduces a latency of 3–5 video lines, or about 0.1–0.2 ms at 4K60, due to the buffering and processing steps. The HDMI input latency includes the TMDS deserialization (1 line), the color space conversion (1 line), and the DSC encoding (1–2 lines). The eDP output latency includes the packetization (0.5 lines) and the link training (5–10 ms startup, but negligible during steady state). The total latency is acceptable for most applications, but for gaming or VR, it can be noticeable. The chip can reduce latency by bypassing the DSC encoder if the bandwidth allows, or by using a smaller buffer. The eDP protocol also includes a feature called “Fast Link Training” that reduces the training time to 1 ms by using pre-stored equalization settings. The bridge chip’s firmware must support this feature to meet low-latency requirements.